Modern communication systems perform a broad range of signal processing functions and tasks such as filtering, channel equalization, signal parameter estimation, transforms, and correlations. Digital signal processors (DSPs) are often preferred for implementing these tasks because DSPs have shorter development cycles and have the flexibility to adapt to changes in system requirements. Traditional DSPs suffer, however, from various drawbacks such as a lack high throughput signal processing capacity and a lack of I/O (input/output) bandwidth. In the past, these shortcomings have been addressed by equipping DSPs with hardware coprocessors or accelerators, and direct memory access (DMA) channels. Adding such additional hardware has increased the cost and complexity of communication systems and still, general purpose DSPs have not demonstrated the throughput or capacity for higher data rates that next generation systems will require. Although increasing processor speed and adding hardware accelerator components help, such solutions are unattractive in terms of development time because they are application-specific and result in increased design complexity. Increased operating speeds also result in an increase in processor power consumption.
The invention of the present application provides a new processor architecture that is especially suitable for rapid handling of operations typically encountered in signal processing applications. The architecture is extremely well suited for performing high throughput signal processing tasks such as parallel (or vector) processing for complex and matrix arithmetic, operations on oversampled complex data with variable dynamic ranges, specialized communications algorithm (e.g., Viterbi) operations, and so forth, and does so without adding significantly to the cost or power consumption of the processor.